There is known a high withstand voltage IC (Integrated Circuit) comprising a plurality of semiconductor devices formed on a common semiconductor substrate, such as a p-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an n-channel MOSFET.
FIG. 5 shows a p-channel MOSFET which constitutes a high withstand voltage IC and FIG. 6 shows an n-channel MOSFET which constitutes a high withstand voltage IC.
As shown in FIG. 5, a p-channel MOSFET 101 includes a p−-type semiconductor substrate 102, an n−-type epitaxial layer 103, a p+-type diffusion isolation layer 104, a p-type diffusion region 105, a p+-type drain contact region 106, a p+-type source region 107 and an n+-type back gate region 108.
The epitaxial layer 103 is formed on the semiconductor substrate 102. The diffusion isolation layer 104 electrically isolates the p-channel MOSFET 101 from other semiconductor devices (e.g., an n-channel MOSFET) by pn junction isolation. The diffusion region 105 is formed at the surface of the epitaxial layer 103 by impurity diffusion. The drain contact region 106 is formed, adjacent to the diffusion region 105, at the surface of the epitaxial layer 103. The source region 107 is formed at the surface of the epitaxial layer 103 with a predetermined distance apart from the diffusion region 105. The back gate region 108 is formed near the source region 107 at the surface of the epitaxial layer 103.
The surface region of the epitaxial layer 103 which lies between the diffusion region 105 and the source region 107 functions as a channel region. A gate electrode 110 is formed at the top surface of the channel region via a gate oxide layer 109. A drain electrode 111 is formed at the top surface of the drain contact region 106, a source electrode 112 is formed at the top surface of the source region 107, a back gate electrode 113 is formed at the top surface of the back gate region 108, and a ground electrode 114 is formed at the top surface of the diffusion isolation layer 104. The electrodes 111, 112, 113 and 114 are electrically connected to the regions 106, 107, 108 and 104, respectively. A field oxide film 115 formed on the diffusion region 105.
As shown in FIG. 6, an n-channel MOSFET 121 includes the semiconductor substrate 102 and the epitaxial layer 103, which are common to the p-channel MOSFET 101, a p+-type diffusion isolation layer 122, a p-type diffusion region 123, a p+-type diffusion region 124, an n+-type drain contact region 125, a p-type diffusion region 126, and an n+-type source region 127.
The diffusion isolation layer 122 electrically isolates the n-channel MOSFET 121 from other semiconductor devices (e.g., a p-channel MOSFET) by pn junction isolation. The diffusion region 123 is formed at the surface of the epitaxial layer 103 by impurity diffusion. The diffusion region 124 is formed, adjacent to the diffusion region 123, at the surface of the epitaxial layer 103. The drain contact region 125 is formed at the surface of the epitaxial layer 103 with a predetermined distance apart from the diffusion region 123. The diffusion region 126 is formed adjacent to the diffusion isolation layer 122. The source region 127 is formed at the surface of the diffusion region 126.
The surface region of the diffusion region 126 which lies between the epitaxial layer 103 and the source region 127 functions as a channel region. A gate electrode 129 is formed at the top surface of the channel region via a gate oxide layer 128. A drain electrode 130 is formed at the top surface of the drain contact region 125, a source electrode 131 is formed at the top surface of the source region 127, and a ground electrode 132 is formed at the top surface of the diffusion isolation layer 122. The electrodes 130, 131 and 132 are electrically connected to the regions 125, 127 and 122, respectively. A field oxide film 133 formed on the diffusion region 123.
As described above, the p-channel MOSFET 101 and the n-channel MOSFET 121 are both have a so-called double RESURF structure where the n−-type epitaxial layer 103 is formed on the p−-type semiconductor substrate 102 and the p-type diffusion region 105, 123 is formed at the surface of the n−-type epitaxial layer 103.
As a voltage is applied between the source electrode 112, 131 and the drain electrode 111, 130, a depletion layer extends from each of a pn junction formed at the interface between the semiconductor substrate 102 and the epitaxial layer 103 and a pn junction formed at the interface between the epitaxial layer 103 and the diffusion region 105, 123.
When the applied voltage reaches a predetermined voltage value, the depletion layers that extend from the two pn junctions are connected together. Accordingly, the depletion layer extends substantially all over the epitaxial layer 103 and the diffusion region 105, 123, thus fixing the potential. As a result, the electric field is relaxed well so that the MOSFET 101, 121 having a high withstand voltage is realized.
To provide a good electric-field relaxing effect in the MOSFET 101, 121 having a double RESURF structure, it is necessary to properly keep the charge balance among the semiconductor substrate 102, the epitaxial layer 103 and the diffusion region 105, 123.
To properly keep the charge balance, it is preferable that when the voltage between the source electrode 112, 131 and the drain electrode 111, 130 reaches the predetermined voltage value, the difference between the total amount of negative fixed charges of the semiconductor substrate 102 and the diffusion region 105, 123 in that region (depletion layer region) where the depletion layer extends and the total amount of positive fixed charges of the epitaxial layer 103 should become small.
It is however difficult to properly keep the charge balance among the semiconductor substrate 102, the epitaxial layer 103 and the diffusion region 105, 123 of the MOSFET 101, 121 having the double RESURF structure.
For example, the thickness of the epitaxial layer 103 between the semiconductor substrate 102 and the diffusion region 105, 123 depends on the diffusion depth of the diffusion region 105, 123. This makes it extremely difficult to design a semiconductor device in such a way as to properly keep the charge balance. Therefore, it is difficult to properly keep the charge balance among the semiconductor substrate 102, the epitaxial layer 103 and the diffusion region 105, 123.
Also high-precision process control is required in the fabrication process for forming each semiconductor region. This makes it difficult to stably produce high withstand voltage ICs having a predetermined withstand voltage with a high yield, thus lowering the productivity of high withstand voltage ICs.
By the way, an MOSFET which has a so-called single RESURF structure where a RESURF region comprised of the diffusion region 105, 123 is not formed involves fewer fabrication processes that requires high-precision process control than an MOSFET which has the double RESURF structure. In other words, the MOSFET having the single RESURF structure has an advantage of a higher productivity over the MOSFET having the double RESURF structure. However, the single RESURF structure has a shortcoming that it is difficult to realize a high withstand voltage, as compared with the double RESURF structure.
In this respect, studies are made on a high withstand voltage IC which makes good use of the merits of the double RESURF structure and the single RESURF structure.
For instance, studies are made on the formation of a p-channel MOSFET having a double RESURF structure and an n-channel MOSFET having a single RESURF structure at a single semiconductor substrate in case where a high withstand voltage IC needs a p-channel MOSFET with a high withstand voltage.
Because of the following reason, however, a p-channel MOSFET having a double RESURF structure and an n-channel MOSFET having a single RESURF structure could not be formed at a single semiconductor substrate.
An n-channel MOSFET and a p-channel MOSFET are formed by a common p−-type semiconductor substrate and a common n−-type epitaxial layer.
If the impurity concentrations of the p−-type semiconductor substrate and the n−-type epitaxial layer are so set as to achieve the charge balance required of an n-channel MOSFET having a relatively high withstand voltage, therefore, the charge balance in the double RESURF structure of the p-channel MOSFET is lost.
Due to the above reason, the single RESURF structure that would not need high-precision process control so much and the double RESURF structure that would be able to achieve a high withstand voltage could not be formed at a single semiconductor substrate.
The invention has been made in consideration of the problem and aims at providing a semiconductor device suitable for a high withstand voltage IC which has high voltage withstandability and high productivity.
The invention also aims at providing a semiconductor device having a double RESURF structure which is suitable for a case where it is formed together with a semiconductor device having a single RESURF structure at a single semiconductor substrate.
Further, the invention aims at providing a semiconductor device having a double RESURF structure which can be formed together with a semiconductor device having a single RESURF structure at a single semiconductor substrate without losing the charge balance.